304 lines
13 KiB
C
304 lines
13 KiB
C
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/******************************** -*- C -*- ****************************
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*
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* Run-time assembler for the SPARC
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*
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***********************************************************************/
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/***********************************************************************
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*
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* Copyright 1999, 2000, 2001, 2002 Ian Piumarta
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*
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* This file is part of GNU lightning.
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*
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* GNU lightning is free software; you can redistribute it and/or modify it
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* under the terms of the GNU Lesser General Public License as published
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* by the Free Software Foundation; either version 2.1, or (at your option)
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* any later version.
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*
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* GNU lightning is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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* License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with GNU lightning; see the file COPYING.LESSER; if not, write to the
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* Free Software Foundation, 59 Temple Place - Suite 330, Boston,
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* MA 02111-1307, USA.
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*
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***********************************************************************/
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#ifndef __lightning_asm_h
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#define __lightning_asm_h
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/* <imm> = [0-9]+ -> add i, one parameter (imm)
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* <reg> = %<imm> -> add r, one parameter (imm or _Rr(imm) )
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* %g<imm> -> add r, one parameter (imm or _Rg(imm) )
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* %o<imm> -> add r, one parameter (imm+8 or _Ro(imm) )
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* %l<imm> -> add r, one parameter (imm+16 or _Rl(imm) )
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* %i<imm> -> add r, one parameter (imm+24 or _Ri(imm) )
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* <mem> = <imm>(<reg>) -> add m, two parameters (reg,imm)
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* <idx> = <reg>(<reg>) -> add x, two parameters (reg,reg)
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*/
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typedef unsigned int jit_insn;
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#define _d30(BD) ((_UL(BD) - _UL(_jit.pc))>>2)
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#define _d22(BD) _ck_d(22, _d30(BD))
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#define _HI(I) (_UL(I) >> (10))
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#define _LO(I) (_UL(I) & _MASK(10))
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/* register names */
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#define _y 0
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#define _psr 1
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#define _Rr(N) ( 0+(N))
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#define _Rg(N) ( 0+(N))
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#define _Ro(N) ( 8+(N))
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#define _Rl(N) (16+(N))
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#define _Ri(N) (24+(N))
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/* instruction formats -- Figure 5-1, page 44 in */
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/* SPARC International, "The SPARC Architecture Manual, Version 8", Prentice-Hall, 1992. */
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#define _0i(RD, OP2, IMM) _I((0<<30)| (_u5(RD)<<25)|(_u3(OP2)<<22)| _u22(IMM))
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#define _0( A, CC, OP2, DSP) _I((0<<30)|(_u1(A)<<29)|(_u4(CC)<<25)|(_u3(OP2)<<22)| _d22(DSP))
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#define _0d( A, CC, OP2, DSP) _I((0<<30)|(_u1(A)<<29)|(_u4(CC)<<25)|(_u3(OP2)<<22)| _u22(DSP))
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#define _1( DSP) _I((1<<30)| _d30(DSP))
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#define _2( RD, OP3, RS1, I, ASI, RS2) _I((2<<30)| (_u5(RD)<<25)|(_u6(OP3)<<19)|(_u5(RS1)<<14)|(_u1(I)<<13)|(_u8(ASI)<<5)|_u5 (RS2))
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#define _2i(RD, OP3, RS1, I, IMM) _I((2<<30)| (_u5(RD)<<25)|(_u6(OP3)<<19)|(_u5(RS1)<<14)|(_u1(I)<<13)| _s13(IMM))
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#define _2f(RD, OP3, RS1, OPF, RS2) _I((2<<30)| (_u5(RD)<<25)|(_u6(OP3)<<19)|(_u5(RS1)<<14)| (_u9(OPF)<<5)|_u5 (RS2))
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#define _3( RD, OP3, RS1, I, ASI, RS2) _I((3<<30)| (_u5(RD)<<25)|(_u6(OP3)<<19)|(_u5(RS1)<<14)|(_u1(I)<<13)|(_u8(ASI)<<5)|_u5 (RS2))
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#define _3i(RD, OP3, RS1, I, IMM) _I((3<<30)| (_u5(RD)<<25)|(_u6(OP3)<<19)|(_u5(RS1)<<14)|(_u1(I)<<13)| _s13(IMM))
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/* basic instructions [Section B, page 87] */
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#define ADDrrr(RS1, RS2, RD) _2 ((RD), 0, (RS1), 0, 0, (RS2))
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#define ADDrir(RS1, IMM, RD) _2i ((RD), 0, (RS1), 1, (IMM))
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#define ADDCCrrr(RS1, RS2, RD) _2 ((RD), 16, (RS1), 0, 0, (RS2))
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#define ADDCCrir(RS1, IMM, RD) _2i ((RD), 16, (RS1), 1, (IMM))
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#define ADDXrrr(RS1, RS2, RD) _2 ((RD), 8, (RS1), 0, 0, (RS2))
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#define ADDXrir(RS1, IMM, RD) _2i ((RD), 8, (RS1), 1, (IMM))
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#define ADDXCCrrr(RS1, RS2, RD) _2 ((RD), 24, (RS1), 0, 0, (RS2))
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#define ADDXCCrir(RS1, IMM, RD) _2i ((RD), 24, (RS1), 1, (IMM))
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#define ANDrrr(RS1, RS2, RD) _2 ((RD), 1, (RS1), 0, 0, (RS2))
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#define ANDrir(RS1, IMM, RD) _2i ((RD), 1, (RS1), 1, (IMM))
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#define ANDCCrrr(RS1, RS2, RD) _2 ((RD), 17, (RS1), 0, 0, (RS2))
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#define ANDCCrir(RS1, IMM, RD) _2i ((RD), 17, (RS1), 1, (IMM))
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#define BNi(DISP) _0 (0, 0, 2, (DISP))
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#define BN_Ai(DISP) _0 (1, 0, 2, (DISP))
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#define BEi(DISP) _0 (0, 1, 2, (DISP))
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#define BE_Ai(DISP) _0 (1, 1, 2, (DISP))
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#define BLEi(DISP) _0 (0, 2, 2, (DISP))
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#define BLE_Ai(DISP) _0 (1, 2, 2, (DISP))
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#define BLi(DISP) _0 (0, 3, 2, (DISP))
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#define BL_Ai(DISP) _0 (1, 3, 2, (DISP))
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#define BLEUi(DISP) _0 (0, 4, 2, (DISP))
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#define BLEU_Ai(DISP) _0 (1, 4, 2, (DISP))
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#define BCSi(DISP) _0 (0, 5, 2, (DISP))
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#define BCS_Ai(DISP) _0 (1, 5, 2, (DISP))
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#define BNEGi(DISP) _0 (0, 6, 2, (DISP))
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#define BNEG_Ai(DISP) _0 (1, 6, 2, (DISP))
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#define BVSi(DISP) _0 (0, 7, 2, (DISP))
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#define BVS_Ai(DISP) _0 (1, 7, 2, (DISP))
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#define BAi(DISP) _0 (0, 8, 2, (DISP))
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#define BA_Ai(DISP) _0 (1, 8, 2, (DISP))
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#define BNEi(DISP) _0 (0, 9, 2, (DISP))
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#define BNE_Ai(DISP) _0 (1, 9, 2, (DISP))
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#define BGi(DISP) _0 (0, 10, 2, (DISP))
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#define BG_Ai(DISP) _0 (1, 10, 2, (DISP))
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#define BGEi(DISP) _0 (0, 11, 2, (DISP))
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#define BGE_Ai(DISP) _0 (1, 11, 2, (DISP))
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#define BGUi(DISP) _0 (0, 12, 2, (DISP))
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#define BGU_Ai(DISP) _0 (1, 12, 2, (DISP))
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#define BCCi(DISP) _0 (0, 13, 2, (DISP))
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#define BCC_Ai(DISP) _0 (1, 13, 2, (DISP))
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#define BPOSi(DISP) _0 (0, 14, 2, (DISP))
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#define BPOS_Ai(DISP) _0 (1, 14, 2, (DISP))
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#define BVCi(DISP) _0 (0, 15, 2, (DISP))
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#define BVC_Ai(DISP) _0 (1, 15, 2, (DISP))
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#define CALLi(DISP) _1 ((DISP))
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#define FLUSHrr(RS1, RS2) _2 (0, 0x3b, (RS1), 0, 0, (RS2))
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#define FLUSHir(IMM, RS1) _2i (0, 0x3b, (RS1), 1, (IMM))
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#define JMPLxr(RS1, RS2, RD) _2 ((RD), 56, (RS1), 0, 0, (RS2))
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#define JMPLmr(RS1, IMM, RD) _2i ((RD), 56, (RS1), 1, (IMM))
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#define LDxr(RS1, RS2, RD) _3 ((RD), 0, (RS1), 0, 0, (RS2))
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#define LDmr(RS1, IMM, RD) _3i ((RD), 0, (RS1), 1, (IMM))
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#define LDUBxr(RS1, RS2, RD) _3 ((RD), 1, (RS1), 0, 0, (RS2))
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#define LDUBmr(RS1, IMM, RD) _3i ((RD), 1, (RS1), 1, (IMM))
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#define LDUHxr(RS1, RS2, RD) _3 ((RD), 2, (RS1), 0, 0, (RS2))
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#define LDUHmr(RS1, IMM, RD) _3i ((RD), 2, (RS1), 1, (IMM))
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#define LDDxr(RS1, RS2, RD) _3 ((RD), 3, (RS1), 0, 0, (RS2))
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#define LDDmr(RS1, IMM, RD) _3i ((RD), 3, (RS1), 1, (IMM))
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#define LDSBxr(RS1, RS2, RD) _3 ((RD), 9, (RS1), 0, 0, (RS2))
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#define LDSBmr(RS1, IMM, RD) _3i ((RD), 9, (RS1), 1, (IMM))
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#define LDSHxr(RS1, RS2, RD) _3 ((RD), 10, (RS1), 0, 0, (RS2))
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#define LDSHmr(RS1, IMM, RD) _3i ((RD), 10, (RS1), 1, (IMM))
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#define ORrrr(RS1, RS2, RD) _2 ((RD), 2, (RS1), 0, 0, (RS2))
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#define ORrir(RS1, IMM, RD) _2i ((RD), 2, (RS1), 1, (IMM))
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#define ORCCrrr(RS1, RS2, RD) _2 ((RD), 18, (RS1), 0, 0, (RS2))
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#define ORCCrir(RS1, IMM, RD) _2i ((RD), 18, (RS1), 1, (IMM))
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#define RDir(RS, RD) _2 ((RD), (RS)|0x28, 0, 0, 0,0)
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#define RESTORErrr(RS1, RS2, RD) _2 ((RD), 61, (RS1), 0, 0, (RS2))
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#define RESTORErir(RS1, IMM, RD) _2i ((RD), 61, (RS1), 1, (IMM))
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#define SAVErrr(RS1, RS2, RD) _2 ((RD), 60, (RS1), 0, 0, (RS2))
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#define SAVErir(RS1, IMM, RD) _2i ((RD), 60, (RS1), 1, (IMM))
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#define SDIVrrr(RS1, RS2, RD) _2 ((RD), 15, (RS1), 0, 0, (RS2))
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#define SDIVrir(RS1, IMM, RD) _2i ((RD), 15, (RS1), 1, (IMM))
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#define SDIVCCrrr(RS1, RS2, RD) _2 ((RD), 31, (RS1), 0, 0, (RS2))
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#define SDIVCCrir(RS1, IMM, RD) _2i ((RD), 31, (RS1), 1, (IMM))
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#define SETHIir(IMM, RD) _0i ((RD), 4, (IMM))
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#define SLLrrr(RS1, RS2, RD) _2 ((RD), 37, (RS1), 0, 0, (RS2))
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#define SLLrir(RS1, IMM, RD) _2i ((RD), 37, (RS1), 1, (IMM))
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#define SMULrrr(RS1, RS2, RD) _2 ((RD), 11, (RS1), 0, 0, (RS2))
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#define SMULrir(RS1, IMM, RD) _2i ((RD), 11, (RS1), 1, (IMM))
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#define SMULCCrrr(RS1, RS2, RD) _2 ((RD), 27, (RS1), 0, 0, (RS2))
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#define SMULCCrir(RS1, IMM, RD) _2i ((RD), 27, (RS1), 1, (IMM))
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#define SRArrr(RS1, RS2, RD) _2 ((RD), 39, (RS1), 0, 0, (RS2))
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#define SRArir(RS1, IMM, RD) _2i ((RD), 39, (RS1), 1, (IMM))
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#define SRLrrr(RS1, RS2, RD) _2 ((RD), 38, (RS1), 0, 0, (RS2))
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#define SRLrir(RS1, IMM, RD) _2i ((RD), 38, (RS1), 1, (IMM))
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#define STrx(RS, RD1, RD2) _3 ((RS), 4, (RD1), 0, 0, (RD2))
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#define STrm(RS, RD, IMM) _3i ((RS), 4, (RD), 1, (IMM))
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#define STBrx(RS, RD1, RD2) _3 ((RS), 5, (RD1), 0, 0, (RD2))
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#define STBrm(RS, RD, IMM) _3i ((RS), 5, (RD), 1, (IMM))
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#define STBAR() _0i (0, 0x28, 15, 0, 0)
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#define STHrx(RS, RD1, RD2) _3 ((RS), 6, (RD1), 0, 0, (RD2))
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#define STHrm(RS, RD, IMM) _3i ((RS), 6, (RD), 1, (IMM))
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#define STDrx(RS, RD1, RD2) _3 ((RS), 7, (RD1), 0, 0, (RD2))
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#define STDrm(RS, RD, IMM) _3i ((RS), 7, (RD), 1, (IMM))
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#define SUBrrr(RS1, RS2, RD) _2 ((RD), 4, (RS1), 0, 0, (RS2))
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#define SUBrir(RS1, IMM, RD) _2i ((RD), 4, (RS1), 1, (IMM))
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#define SUBCCrrr(RS1, RS2, RD) _2 ((RD), 20, (RS1), 0, 0, (RS2))
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#define SUBCCrir(RS1, IMM, RD) _2i ((RD), 20, (RS1), 1, (IMM))
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#define SUBXrrr(RS1, RS2, RD) _2 ((RD), 12, (RS1), 0, 0, (RS2))
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#define SUBXrir(RS1, IMM, RD) _2i ((RD), 12, (RS1), 1, (IMM))
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#define SUBXCCrrr(RS1, RS2, RD) _2 ((RD), 28, (RS1), 0, 0, (RS2))
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#define SUBXCCrir(RS1, IMM, RD) _2i ((RD), 28, (RS1), 1, (IMM))
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#define UDIVrrr(RS1, RS2, RD) _2 ((RD), 14, (RS1), 0, 0, (RS2))
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#define UDIVrir(RS1, IMM, RD) _2i ((RD), 14, (RS1), 1, (IMM))
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#define UDIVCCrrr(RS1, RS2, RD) _2 ((RD), 30, (RS1), 0, 0, (RS2))
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#define UDIVCCrir(RS1, IMM, RD) _2i ((RD), 30, (RS1), 1, (IMM))
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#define UMULrrr(RS1, RS2, RD) _2 ((RD), 10, (RS1), 0, 0, (RS2))
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#define UMULrir(RS1, IMM, RD) _2i ((RD), 10, (RS1), 1, (IMM))
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#define UMULCCrrr(RS1, RS2, RD) _2 ((RD), 26, (RS1), 0, 0, (RS2))
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#define UMULCCrir(RS1, IMM, RD) _2i ((RD), 26, (RS1), 1, (IMM))
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#define WRrri(RS1, RS2, RD) _2 (0, (RD)|0x30, RS1, 0, 0, (RS2))
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#define WRrii(RS1, IMM, RD) _2i (0, (RD)|0x30, RS1, 1, (IMM))
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#define XORrrr(RS1, RS2, RD) _2 ((RD), 3, (RS1), 0, 0, (RS2))
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#define XORrir(RS1, IMM, RD) _2i ((RD), 3, (RS1), 1, (IMM))
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#define XORCCrrr(RS1, RS2, RD) _2 ((RD), 19, (RS1), 0, 0, (RS2))
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#define XORCCrir(RS1, IMM, RD) _2i ((RD), 19, (RS1), 1, (IMM))
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/* synonyms */
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#define Bi(DISP) BAi((DISP))
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#define B_Ai(DISP) BA_Ai((DISP))
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#define BNZi(DISP) BNEi((DISP))
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#define BNZ_Ai(DISP) BNE_Ai((DISP))
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#define BZi(DISP) BEi((DISP))
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#define BZ_Ai(DISP) BE_Ai((DISP))
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#define BGEUi(DISP) BCCi((DISP))
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#define BGEU_Ai(DISP) BCC_Ai((DISP))
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#define BLUi(DISP) BCSi((DISP))
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#define BLU_Ai(DISP) BCS_Ai((DISP))
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#define LDUWxr(RS1, RS2, RD) LDxr((RS1), (RS2), (RD))
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#define LDUWmr(RS1, IMM, RD) LDmr((RS1), (IMM), (RD))
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#define LDSWxr(RS1, RS2, RD) LDxr((RS1), (RS2), (RD))
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#define LDSWmr(RS1, IMM, RD) LDmr((RS1), (IMM), (RD))
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#define STWrx(RS, RD1, RD2) STrx((RS), (RD1), (RD2))
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#define STWrm(RS, RD, IMM) STrm((RS), (RD), (IMM))
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/* synthetic instructions [Table A-1, page 85] */
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#define BCLRrr(R,S) ANDNrrr((R), (S), (S))
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#define BCLRir(I,R) ANDNrir((R), (I), (R))
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#define BSETrr(R,S) ORrrr((R), (S), (S))
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#define BSETir(I,R) ORrir((R), (I), (R))
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#define BTOGrr(R,S) XORrrr((R), (S), (S))
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#define BTOGir(I,R) XORrir((R), (I), (R))
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#define BTSTrr(R,S) ANDCCrrr((R), (S), 0)
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#define BTSTir(I,R) ANDCCrir((R), (I), 0)
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#define CALLm(R,I) JMPLmr((R), (I), _Ro(7))
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#define CALLx(R,S) JMPLxr((R), (S), _Ro(7))
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#define CLRr(R) ORrrr(0, 0, (R))
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#define CLRBm(R,I) STBrm(0, (R), (I))
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#define CLRBx(R,S) STBrm(0, (R), (S))
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#define CLRHm(R,I) STHrm(0, (R), (I))
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#define CLRHx(R,S) STHrm(0, (R), (S))
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#define CLRm(R,I) STrm(0, (R), (I))
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#define CLRx(R,S) STrm(0, (R), (S))
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#define CMPrr(RS1, RS2) SUBCCrrr((RS1), (RS2), 0)
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#define CMPri(RS1, IMM) SUBCCrir((RS1), (IMM), 0)
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#define DECr(R) SUBrir((R), 1, (R))
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#define DECir(I,R) SUBrir((R), (I), (R))
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#define DECCCr(R) SUBCCrir((R), 1, (R))
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#define DECCCir(I,R) SUBCCrir((R), (I), (R))
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#define INCr(R) ADDrir((R), 1, (R))
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#define INCir(I,R) ADDrir((R), (I), (R))
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#define INCCCr(R) ADDCCrir((R), 1, (R))
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#define INCCCir(I,R) ADDCCrir((R), (I), (R))
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#define JMPm(R,I) JMPLmr((R), (I), 0)
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#define JMPx(R,S) JMPLxr((R), (S), 0)
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#define MOVrr(R,S) ORrrr(0, (R), (S))
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#define MOVir(I, R) ORrir(0, (I), (R))
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#define NEGrr(R,S) SUBrrr(0, (R), (S))
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#define NEGr(R) SUBrrr(0, (R), (R))
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#define NOP() SETHIir(0, 0)
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#define NOTrr(R,S) XNORrrr((R), 0, (S))
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#define NOTr(R) XNORrrr((R), 0, (R))
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#define RESTORE() RESTORErrr(0, 0, 0)
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#define RET() JMPLmr(_Ri(7),8 ,0)
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#define RETL() JMPLmr(_Ro(7),8 ,0)
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#define SAVE() SAVErrr(0, 0, 0)
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#define SETir(I,R) (_siP(13,(I)) ? MOVir((I),(R)) : SETir2(_HI(I), _LO(I), (R)))
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#define SETir2(H,L,R) (SETHIir(H,R), (L ? ORrir(R,L,R) : 0))
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/* BNZ,a executes the delay instruction if NZ (so skips if Z)
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||
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* BZ,a executes the delay instruction if Z (so skips if NZ). */
|
||
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#define SKIPZ() _0d (1, 9, 2, 2) /* BNZ,a .+8 */
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||
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#define SKIPNZ() _0d (1, 1, 2, 2) /* BZ,a .+8 */
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||
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#define SKIP() _0d (1, 0, 2, 0) /* BN,a . */
|
||
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#define TSTr(R) ORCCrrr(0, (R), 0)
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||
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#define WRii(IMM, RD) WRrii(0, (IMM), (RD))
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||
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#define WRri(RS2, RD) WRrri(0, (RS2), (RD))
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||
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#endif /* __ccg_asm_sparc_h */
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